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G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
Features :
4,194,304 words by 4 bits organization. Fast access time and cycle time Low power dissipation. Read-Modify-Write, RAS -Only Refresh,
CAS -Before- RAS Refresh, Hidden Refresh.
Description :
The GLT4160L04 is a high-performance CMOS dynamic random access memory containing 16,777,216 bits organized in a x4 configuration. The GLT4160L04 offers page cycle access with Extended Data Output. The GLT4160L04 has 11 row- and 11 column-addresses, and accepts 2048-cycle refresh in 32 ms. The GLT4160L04 provides EDO PAGE MODE operation which allows for fast data access within a row-address defined boundary, up to 2048 x 4 bits with cycle times as short as 18ns.
2,048 refresh cycles per 32ms. Available in 300 mil 26(24) SOJ and TSOPII.
3.3V0.3V Vcc Power Supply voltage.
All inputs and Outputs are LVTTL compatible. Extended Data-Out (EDO) Page access cycle. Self-refresh Capability. (S-Version).
HIGH PERFORMANCE Max. RAS Access Time, (tRAC) Max. Column Address Access Time, (tAA) Min. Extended Data Out Page Mode Cycle Time, (tPC) Min. Read/Write Cycle Time, (tRC) Max. CAS Access Time (tCAC)
40 40 ns 20 ns 18 ns 70 ns 12 ns
50 50 ns 25 ns 20 ns 84 ns 13 ns
60 60 ns 30 ns 25 ns
70 70 ns 35 ns 30 ns
104 ns 124 ns 15 ns 20 ns
G-Link Technology
2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan.
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G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
Pin Configuration :
GLT4160L04 300mil 26(24) SOJ
Vcc DQ0 DQ1 WE RAS NC A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 8 9 10 11 12 13 26 25 24 23 22 21 19 18 17 16 15 14 VSS DQ3 DQ2 CAS OE A9 A8 A7 A6 A5 A4 VSS Vcc DQ0 DQ1 WE RAS NC A10 A0 A1 A2 A3 VCC
GLT4160L04 300mil 26(24) TSOPII
1 2 3 4 5 6 8 9 10 11 12 13 26 25 24 23 22 21 19 18 17 16 15 14 VSS DQ3 DQ2 CAS OE A9 A8 A7 A6 A5 A4 VSS
Pin Descriptions: Name A0 - A10
RAS CAS WE OE
Function Address Inputs Row Address Strobe Column Address Strobe Write Enable Output Enable Data Inputs / Outputs +3.3V Power Supply Ground No Connection
DQ0 - DQ3 VCC VSS NC
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G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan.
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G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
Absolute Maximum Ratings*
Capacitance*
TA=25C, VCC=3.3V0.3V, VSS=0V Max. Unit 5 7 7 pF pF pF
Operating Temperature, TA (ambient) Symbol Parameter .................................................0C to +70C CIN1 Address Input For Extended Temperature.................-20C to 85C CIN2 RAS, CAS, WE, OE Storage Temperature(plastic)............-55C to +150C Voltage Relative to VSS........................-0.5V to + 4.6V COUT Data Input/Output Short Circuit Output Current...............................20mA Power Dissipation...............................................1.0W
*Note: Operation above Absolute Maximum Ratings can aversely affect device reliability.
*Note: Capacitance is sampled and not 100% tested
Electrical Specifications
l l
All voltages are referenced to GND. After power up, wait more than 200s and then, execute eight CAS -before- RAS or RAS -only refresh cycles as dummy cycles to initialize internal circuit.
Block Diagram :
WE CAS DATA-IN BUFFER 4 DQ0 DQ1 DQ2 DQ3
NO.2 CLOCK GENERATOR
DATA-OUT BUFFER
4 4
OE COLUMNADDRESS BUFFER(11) 11 COLUMN DECODER 2048 REFRESH CONTROLLER SENSE AMPLIFIERS I/O GATING 4
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
11
REFRESH COUNTER
2048
11
ROW ADDRESS BUFFERS(11)
ROW DECODER
11
2048
2048 x 1024 x 4 MEMORY ARRAY
RAS
NO.1 CLOCK GENERATOR
VDD VSS
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G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan.
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G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
Truth Table:
Function Standby READ EARLY WRITE READ WRITE EDO-PAGE-MODE READ EDO-PAGE-MODE EARLY-WRITE EDO-PAGE-MODE READ-WRITE
RAS -ONLY REFRESH
RAS
H L L L 1st Cycle 2nd cycle 1st Cycle 2nd cycle 1st Cycle 2nd cycle L L L L L L L READ LHL HL HL
CAS
HX L L L HL HL HL HL HL HL H L L L L
WE
X H L HL H H L L HL HL X H L H H
OE
X L X LH L L X X LH LH X L X X X
ADDRESS tR tC X ROW ROW ROW ROW n/a ROW n/a ROW n/a ROW ROW ROW X X X COL COL COL COL COL COL COL COL COL n/a COL COL X X
DATA-IN/OUT DQ1-DQ4 High-Z Data-Out Data-In Data-Out,Data-In Data-Out Data-Out Data-In Data-In Data-Out,Data-In Data-Out,Data-In High-Z Data-Out Data-In High-Z High-Z
HIDDEN REFRESH CBR REFRESH SELF REFRESH
WRITE LHL
G-Link Technology
2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan.
-4-
G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
DC and Operating Characteristics (1-2)
TA = 0C to 70C, -20C to 85C VCC=3.3V0.3V, VSS=0V, unless otherwise specified.
Sym.
ILI
Parameter
Input Leakage Current (any input pin) Output Leakage Current (for High-Z State) Operating Current, Random READ/WRITE
Test Conditions
0V VIN VCC+0.3V (All other pins not under test=0V) 0V Vout VCC Output is disabled (Hiz) tRC = tRC (min.)
Access Time
Min.
-5
Typ
Max.
+5
Unit Notes
A
ILO ICC1
-5 tRAC = 40ns tRAC = 50ns tRAC = 60ns tRAC = 70ns
+5 130 120 80 70 1
A 1,2 mA
ICC2
Standby Current (TTL)
RAS , CAS at VIH other inputs VSS RAS cycling, CAS at VIH
tRC = tRC (min.) tRAC = 40ns tRAC = 50ns tRAC = 60ns tRAC = 70ns tRAC = 40ns tRAC = 50ns tRAC = 60ns tRAC = 70ns tRAC = 40ns tRAC = 50ns tRAC = 60ns tRAC = 70ns
mA 2 mA
ICC3
Refresh Current,
RAS -Only
ICC4 Operating Current, EDO Page Mode
RAS at VIL, CAS address
cycling:tPC=tPC(min.)
ICC5
Refresh Current,
RAS , CAS address cycling:
tRC=tRC (min.)
CAS Before RAS
ICC6 Standby Current, (CMOS)
130 120 80 70 130 120 80 70 130 120 80 70
1,2 mA
mA
1
RAS VCC-0.2V, CAS VCC-0.2V, All other inputs VSS
300 A 1,5
ICC7
Self refresh Current
RAS = CAS =0.2V,
WE = OE = A0~A10=VCC-0.2V or 0.2V DQ0~DQ3=VCC-0.2V,0.2V or Open 300 A
VIL VIH VOL VOH
Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
-0.3 2.0 IOL = 2mA IOH = -2mA 2.4
+0.8 VCC+0.3 0.4
V V V V
3 4
Notes:
1. ICC is dependent on output loading when the device output is selected. Specified ICC(max.) is measured with the output open. 2. ICC is dependent upon the number of address transitions specified ICC(max.) is measured with a maximum of one transition per address cycle in random Read/Write and EDO Fast Page Mode. 3. Specified VIL(min.) is steady state operation. During transitions VIL(min.) may undershoot to -1V for a period not to exceed 15ns. All AC parameters are measured with VIL(min.)VSS and VIH(max.)VCC. 4. Specified VIH(max.) is steady state operation . During transitions VIH(max.) may overshoot to VCC+1V for a period not to exceed 15ns. All AC parameters are measured with VIL(min.) VSS and VIH(max.) VCC . 5. S-Version.
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2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan.
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G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
AC Characteristics
TA =0C to 70C , -20C to 85C VCC = 3.3 V 0.3V, VIH/VIL = 3/0 V, VOH/VOL = 2/0.8V An initial pause of 200 s and 8 CAS -before- RAS or RAS -only refresh cycles are required after power-up.
40 50 84 116 30 10K 40 12 20 0 3 12 34 7 18 13 5 0 8 0 6 20 34 0 0 0 0 6 6 12 8 10k 28 20 8 3 3 13 38 8 20 15 5 0 10 0 8 25 40 0 0 0 0 10 10 13 8 10k 37 25 13 50 10k 50 13 25 3 3 15 45 10 20 15 5 0 10 0 10 30 45 0 0 0 0 10 10 15 10 10k 45 30 15 60 104 140 40 60 10k 60 15 30 3 3 20 50 15 20 15 5 0 10 0 15 35 50 0 0 0 0 15 15 30 15 10k 50 35 20 70 124 170 50 70 10k 70 20 35 ns ns ns ns ns 1,2,3
Parameter
Read or Write Cycle Time Read Modify Write Cycle Time RAS Precharge Time RAS Pulse Width Access Time from RAS Access Time from CAS Access Time from Column Address CAS to Output Low-Z CAS to Output High-Z RAS Hold Time CAS Hold Time CAS Pulse Width RAS to CAS Delay Time RAS to Column Address Delay Time CAS to RAS Precharge Time Row Address Set-Up Time Row Address Hold Time Column Address Set-Up Time Column Address Hold Time Column Address to RAS Lead Time Column Address Hold Time Referenced to RAS Read Command Set-Up Time Read Command Hold Time Referenced to CAS Read Command Hold Time Referenced to RAS Write Command Set-Up Time Write Command Hold Time Write Command Pulse Width Write Command to RAS Lead Time Write Command to CAS Lead Time
Symbol Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes
tRC tRWC tRP tRAS tRAC tCAC tAA tCLZ tCEZ tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tAR tRCS tRCH tRRH tWCS tWCH tWP tRWL tCWL
70 91 25 40
ns 1,5,10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4 4 8,9 7 1,5,6
G-Link Technology
2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan.
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G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
AC Characteristics
40 50 0 8 40 67 30 42 47 5 20 22 18 50 6 40 30 12 8 3 3 15 7 3 3 3 5 5 5 5 5 8 10 8 13 3 3 15 13 5 3 3 5 5 5 5 5 13 13 13 100k 20 47 8 50 30 13 15 0 3 15 15 5 3 3 5 5 5 5 5 15 15 15 100k 28 25 56 10 60 35 15 100k 0 10 45 79 34 49 54 5 20 35 30 71 10 70 40 0 20 0 3 20 20 5 3 3 5 5 5 5 5 20 20 20 20 60 0 15 50 94 44 59 64 5 25 40 70 ns ns ns ns ns ns ns ns ns ns ns ns ns 100k ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 8
Parameter
Data Set-Up Time Data Hold Time Data Hold Time Referenced to RAS RAS to WE Delay Time CAS to WE Delay Time Column Address to WE Delay Time CAS Precharge to WE Delay RAS to CAS Precharge Time CAS precharge time ( CAS Before RAS counter test cycle) Access Time from CAS Precharge EDO Page Mode Cycle Time EDO Page Mode Read-Modify-Write Cycle Time CAS Precharge Time (EDO Page Mode) RAS Pulse Width (EDO Page Mode Only) RAS Hold Time from CAS precharge Access Time from OE OE to Data Delay Time OE to Output Low-Z OE to Output High-Z WE to Data Delay OE Command Hold Time Data Output Hold after CAS low RAS to Output High-Z WE to Output High-Z OE to CAS Hold Time CAS Hold Time to OE OE Precharge Time WE Puts width (EDO mixed read write cycle) CAS Set-Up Time for CAS -before- RAS Cycle
Symbol Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes
tDS tDH tDHR tRWD tCWD tAWD tCPWD tRPC tCPT tCPA tPC tPRWC tCP tRASP tRHCP tOEA tOED tOLZ tOEZ tWED tOEH tDOH tREZ tWEZ tOCH tCHO tOEP tWPE tCSR
0 7 36 54 24 32 47 0 20
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G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan.
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G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
40
50 10 10 10 50 32 2 50 32 128 100 90 -50 10 10 10 2
60 15 10 10 50 32 128 100 110 -50 2
70 ns ns ns 50 32 128 100 130 -50 ns ms ms s ns ns
Parameter
CAS Hold Time for CAS -before- RAS Cycle WE to RAS precharge time ( CAS Before RAS refresh ) WE to RAS hold time ( CAS Before RAS refresh ) Transition Time Refresh Period (2,048 cycles) Refresh Period (S-Version) RAS Pulse Width ( CAS Before RAS Self refresh ) RAS precharge Time ( CAS Before RAS Self refresh ) CAS Hold Time ( CAS Before RAS Self refresh )
Symbol Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes tCHR tWRP tWRH tT tREF tREF tRASS tRPS tCHS
100 70 -50 8 10 10 2
128
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G-Link Technology Corporation,Taiwan
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G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
TEST MODE CYCLE
40 50 89 121 55 18 30 55 13 18 43 30 35 72 47 52 25 53 55 100k 33 18 18 18 10 10 18 18 10 10 10k 10k 55 13 18 43 30 35 72 47 52 25 53 55 100k 33 18 20 20 10 10 55 18 30 10k 10k 65 15 20 50 35 39 84 54 59 30 61 65 100k 40 20 25 25 10 10 60 109 145 65 20 35 10k 10k 75 20 25 55 40 49 99 64 69 35 76 75 100k 45 25 70 Notes 129 175 75 25 40 10k 10k ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 8 8 8 8 1,2,3,7 1,3,7 1,2,7
Parameter
Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address RAS pulse width CAS pulse width RAS hold time CAS hold time Column address to RAS lead time CAS to WE delay time RAS to WE delay time Column address to WE delay time CAS Precharge to WE delay time EDO Page Mode cycle time EDO page mode read-modify-write cycle time RAS Pulse width (EDO page cycle) Access time form CAS precharge OE access time OE to data delay OE command hold time Write command set-up time (Test mode in) Write command hold time (Test mode in)
Symbol Min. Max. Min. Max. Min. Max. Min. Max. Unit
tRC tRWC tRAC tCAC tAA tRAS tCAS tRSH tCSH tRAL tCWD tRWD tAWD tCPWD tPC tPRWC tRASP tCPA tOEA tOED tOEH tWTS tWTH
89 121
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2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan.
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G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
Notes:
1. Measure with a load equivalent to one TTL input and 100 pF. 2. Assumes that tRCD tRCD (max.). If tRCD is greater than tRCD (max.), access time will be tAA dominant. 3. Assumes that tRAD tRAD (max.). If tRAD is greater than tRCD (max.), access time will be controlled by tCAC. 4. Either tRRH or tRCH must be satisfied for a Read Cycle. 5. Access time is determined by the longest of tAA, tCAC and tCPA. 6. Assumes that tRAD tRAD (max.). 7. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, the access time is controlled by tCAA and tCAC. 8. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters. 9. tWCS (min.) must be satisfied in an Early Write Cycle. 10. tDS and tDH are referenced to the latter occurrence of CAS or WE . 11. tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 2 ns.
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G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan.
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G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
Read CYCLE
tRC tRAS
VIH-
tRP
RAS
VIL-
tCRP
VIH-
tCSH tRCD tRSH tCAS
tCRP
CAS
VIL-
tASR Address
VIHVIL-
tRAD tRAH
tASC
tRAL tCAH
COLUMN ADDRESS
ROW ADDRESS
tAR tRCS
VIH-
tRCH tRRH
WE
VIL-
tAA
VIH-
tCEZ tOEZ tOEA
OE
VIL-
tRAC DQ
VOHVOL-
tCAC tCLZ
DATA-OUT
Don't Care
Early Write Cycle
NOTE : DOUT = OPEN
tRC
VIH-
tRP
RAS
tRAS
VIL-
tCSH tCRP CAS
VIHVIL-
tRCD
tRSH tCAS
tCRP
VIH-
tASR tRAH
ROW ADDRESS
tRAD tASC
tRAL tCAH
COLUMN ADDRESS
Address
VIL-
tCWL tRWL tAR
VIH-
tWCS
WE
tWCR tWCH tWP
VIL-
VIH-
OE
VIL-
tDHR tDS
VIH-
tDH
DATA - IN
DQ
VIL-
Don't Care
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2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan.
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G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
OE Controlled Write Cycle NOTE : DOUT = OPEN
tRC
VIH-
tRP
RAS
tRAS
VIL-
tCSH tCRP CAS
VIHVIL-
tRCD
tRSH tCAS
tCRP
VIH-
tASR tRAH
ROW ADDRESS
tRAD tASC
tRAL tCAH
COLUMN ADDRESS
Address
VIL-
tCWL tRWL tRCS
VIH-
WE
tWP
VIL-
VIH-
OE
tOEH tOED tDS tDH
DATA - IN
VIL-
VIH-
DQ
VIL-
Don't Care
Read - Modify - Write Cycle
tRC tRP VIHVILtRAS
RAS
tCRP
tRCD
tRSH tCAS tCSH
tCRP
CAS
VIHVILtRAD tASC tCAH COLUMN ADDRESS tAWD tCWD VIHVIL-
tASR VIHVILtRAH ROW ADDR.
Address
tRWL tCWL tWP
WE
OE
VIHVIL-
tOEA tCLZ tAA tOED tOEZ
tCAC
tDS
tDH VALID DATA-IN Don't Care
DQ
VI/OHVI/OLtRAC
VALID DATA-OUT
G-Link Technology
2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan.
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G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
EDO Page Mode Read Cycle NOTE : DOUT = OPEN
tRASP
VIH-
tRP tRHCP
RAS
VIL-
tCSH tCRP
VIH-
tPC tCAS tCP tCAS tCP
tPC tCP tCAS
tPC
tRCD
CAS
VIL-
tCAS
tRAD tCSR tRAH tASC tCAH tASC
COLUMN ADDRESS
tCAH
COLUMN ADDRESS
tASC
tCAH tASC
COL. ADDR.
tCAH
COL. ADDR.
VIH-
Address
VIL-
ROW ADDR.
tRCS
VIH-
tRRH tRCH tAA tCPA tCAC tOCH tOEA tOEP tOEZ tCAC tAA tCPA tCPA tCAC tAA tCHO tOEP
WE
VIL-
VIH-
tOEA tCAC tRAC tOLZ tCLZ
OE
VIL-
tDOH
VALID DATA-OUT
tOEZ
VALID DATA-OUT
tOEZ
VALID DATA-OUT
DQ
VOHVOL-
VALID VALID DATA-OUT DATA-OUT
Don't Care
EDO Page Mode Early Write Cycle NOTE : DOUT = OPEN
tRASP
VIH-
tRP tRHCP
RAS
VIL-
tPC tCRP
VIH-
tPC tCAS tCP tRSH tCAS
tRCD
tCAS
tCP
CAS
VIL-
tRAD tASR Address
VIHVILROW ADDR.
tCSH tCAH
COLUMN ADDRESS
tRAH tASC
tASC
tCAH
tASC
COLUMN ADDRESS
tCAH
COLUMN ADDRESS
tWCS
VIH-
tWCH tWP
tWCS tWP
tWCH
tWCS
tWCH tWP
WE
VIL-
VIH-
OE
VIL-
tDS
VIH-
tDH
VALID DATA-IN
tDS
VALID DATA-IN
tDS
tDS
VALID DATA-IN
tDS
DQ
VIL-
Don't Care
G-Link Technology
2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan.
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G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
EDO Page Mode Read - Modify - Write Cycle NOTE : DOUT = OPEN
tRASP RAS
VIHVIL-
tRP
tCSH tRSH tCAS
tRCD
VIH-
tCAS
tCP
tCRP
CAS
VIL-
tASR
VIH-
tRAD tRAH tASC
tCAH tASC
COL. ADDR. COL. ADDR.
tPRWC tRAL tCAH
Address
VIL-
ROW ADDR.
tRCS
VIH-
tCWL tCWD tAWD tRWD tWP tCWD tAWD tCPWD
WE
tRWL tCWL tWP
VIL-
tOEH tDH tOED tOEZtDS tOEA tCAC tAA tOED tOEZ tDH tDS
OE
VIHVIL-
tOEA tCAC tAA tRAC
VI/OH-
DQ
VI/OL-
tCLZ
VALID DATA-OUT VALID DATA-IN
tCLZ
VALID DATA-OUT VALID DATA-IN Don't Care
EDO PAGE READ AND WRITE MIXED CYCLE
tRASP RAS
VIHVIL-
tRP
CAS
VIHVIL-
tRAH tASC tCAS tASR tCAH
COL. ADDR
tHPC tCP tCP
tHPC tCP tCAS
tHPC tCAS tASC tCAH
tASC
COLUMN ADDRESS
tCAH
tASC
tCAH
ADDRESS
VIHVILVIHVIL-
ROW ADDR
COLUMN ADDRESS
COLUMN ADDRESS
tRCS WE
tRCH
tRCS
tRCH tWCS tWCH
tRCH
tWPE OE
VIHVIL-
tCLZ tWED tDH tDS
VALID DATA-IN
tCPA tOEA tCAC tWEZ tAA
tWEZ
VALID DATA-OUT
tAA
tREZ
VALID DATA-OUT
DQ0~DQ3 VI/OL-
VI/OH-
tRAC
VALID DATA-OUT
Don't Care
G-Link Technology
2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan.
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G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
CAS - Before - RAS Refresh Cycle
tRC tRAS
VIH-
tRC tRP tRAS tRP
RAS
VIL-
tCSR
VIH-
tCHR
tRPC
tCSR
tCHR
tRPC
tCRP
CAS
VIL-
tWRP
VIH-
tWRH
tWRP
tWRH
WE
VIL-
Remark Address, OE : Don't care DQ : Hi - Z
RAS -Only Refresh Cycle
tRC tRAS RAS
VIHVIL-
tRC tRP tRAS tRP
tCRP
VIH-
tRPC
tCRP
CAS
VIL-
tASR
VIH-
tRAH
tASR
tRAH
Address
VIL-
ROW ADDRESS
ROW ADDRESS
Remark
WE, OE : Don't care DQ : Hi - Z
Hidden Refresh Cycle ( Read )
tRC tRAS RAS
VIHVIL-
tRC tRP tRAS tRP
tCRP
VIH-
tRCD
tRSH
tCHR
UCAS,LCAS
VIL-
tRAD tASR Address
VIHVIL-
tRAL tASC tCAH
tCAH
ROW ADDRESS
COLUMN ADDRESS
tRCS
VIH-
tRRH
tWRP
tWRH
WE
VIL-
tAA tOEA
VIH-
OE
VIL-
tCAC tRAC
VIH-
tCLZ
tWEZ tOEZ
DATA-OUT
tCEZ tREZ
DQ
VIL-
OPEN
Don't Care
G-Link Technology
2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan.
- 15 -
G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
Hidden Refresh Cycle ( Write ) NOTE : DOUT = OPEN
tRAS RAS
VIHVIL-
tRC tRP
tRAS
tRP
tCRP
VIH-
tRCD
tRSH
tCHR
CAS
VIL-
tRAD tASC Address
VIHVIL-
tRSH tASC tCAH
tCAH
ROW ADDRESS
COLUMN ADDRESS
tWCS
VIH-
tWCH tWP
tWRP
tWRH
WE
VIL-
VIH-
OE
VIL-
tDS DQ
VIHDATA-IN
tDH
VIL-
Don't Care
G-Link Technology
2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan.
- 16 -
G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
CAS-Before RAS Refresh Counter Test Cycle
tRAS
VIHRAS VIL-
tRP
tCSR
VIHCAS VIL-
tCHR
tCPT
tRSH tCAS tRAL tCAH
tASC Address VIHVILCOLUMN ADDRESS
Read Cycle
WE VILOE VILVIH-
tWRP
tWRH
tRCS
tAA tCAC
tRRH tRCH
VIH-
tOEA tCLZ tOEZ
VALID DATA-OUT
tCEZ
DQ VOL-
VOH-
Write Cycle
VIHWE VIL-
tWRP
tWRH tWCS
tRWL tCWL tWCH tWP
OE VIL-
VIH-
tDS
VIHDQ VIL-
tDH
VALID DATA-IN
OPEN tRCS tWRH
Read-Modify-Write
WE VILVIH-
tAWD tCWD tCAC tAA tOEA tOED tCLZ tOEZ
tCWL tRWL tWP
tWRP
OE VIL-
VIH-
tDH tDS
DQ VI/OL-
VI/OH-
VALID DATA-OUT
VALID DATA-IN
Don't Care
G-Link Technology
2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan.
- 17 -
G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
TEST MODE IN CYCLE
tRC tRP RAS
VIHVILVIHVIL-
tRP tRAS tRPC tCHR
tRPC tCP tCSR
CAS
tWTS WE
VIHVIL-
tWTH
tCEZ
VI/OHDQ VI/OLOPEN
Don't Care
Test Mode
By using the test mode, the test time can be reduced. The reason for this is that, the memory emulates the x 16-bit organization during test mode. Don't care about the input levels of the CAS input A0, A1 . (1) Setting the mode Executing the test mode cycle (WE , CAS before RAS refresh cycle ) sets the test mode. (2) Write / read operation When either a "0" or a "1" is written to the input pin in test mode, this data is written to 16 bits of memory cell. Next, when the data is read from the output pin at the same address, the cell be checked. Output = "1" Normal write (all memory cells) Output = "0" Abnormal write (3) Refresh Refresh in the test mode must be performed with the RAS / CAS cycle or with the WE, CAS before RAS refresh cycle. The WE, CAS before RAS refresh cycle use the same counter as the CAS before RAS refresh's internal counter. (4) Mode Cancellation The test mode is cancelled by executing one cycle of RAS only refresh cycle or CAS before RAS refresh cycle.
G-Link Technology
2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan.
- 18 -
G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
CAS-BEFORE-RAS SELF REFRESH CYCLE
tRP RAS
VIHVILVIHVIL-
tRASS
tRPS tRPC
tRPC tCP tCSR tCHS
CAS
tCEZ DQ
VI/OHVI/OLOPEN
tWRP WE
VIHVIL-
tWRH
Don't Care
NOTE : OE , Address = Don't Care
G-Link Technology
2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan.
- 19 -
G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
Ordering Information
Part Number
GLT4160L04-40J3 GLT4160L04-50J3 GLT4160L04-60J3 GLT4160L04-70J3 GLT4160L04E-40J3 GLT4160L04E-50J3 GLT4160L04E-60J3 GLT4160L04E-70J3 GLT4160L04S-40J3 GLT4160L04S-50J3 GLT4160L04S-60J3 GLT4160L04S-70J3 GLT4160L04SE-40J3 GLT4160L04SE-50J3 GLT4160L04SE-60J3 GLT4160L04SE-70J3 GLT4160L04-40TC GLT4160L04-50TC GLT4160L04-60TC GLT4160L04-70TC GLT4160L04E-40TC GLT4160L04E-50TC GLT4160L04E-60TC GLT4160L04E-70TC GLT4160L04S-40TC GLT4160L04S-50TC GLT4160L04S-60TC GLT4160L04S-70TC GLT4160L04SE-40TC GLT4160L04SE-50TC GLT4160L04SE-60TC GLT4160L04SE-70TC
SPEED
40ns 50ns 60ns 70ns 40ns 50ns 60ns 70ns 40ns 50ns 60ns 70ns 40ns 50ns 60ns 70ns 40ns 50ns 60ns 70ns 40ns 50ns 60ns 70ns 40ns 50ns 60ns 70ns 40ns 50ns 60ns 70ns
POWER
Normal Normal Normal Normal Normal Normal Normal Normal Self Refresh Self Refresh Self Refresh Self Refresh Self Refresh Self Refresh Self Refresh Self Refresh Normal Normal Normal Normal Normal Normal Normal Normal Self Refresh Self Refresh Self Refresh Self Refresh Self Refresh Self Refresh Self Refresh Self Refresh
FEATURE
EDO EDO EDO EDO EDO EDO EDO EDO EDO EDO EDO EDO EDO EDO EDO EDO EDO EDO EDO EDO EDO EDO EDO EDO EDO EDO EDO EDO EDO EDO EDO EDO
TEMPERATURE
Commercial Commercial Commercial Commercial Extended Extended Extended Extended Commercial Commercial Commercial Commercial Extended Extended Extended Extended Commercial Commercial Commercial Commercial Extended Extended Extended Extended Commercial Commercial Commercial Commercial Extended Extended Extended Extended
PACKAGE
SOJ 300mil 26(24)L SOJ 300mil 26(24)L SOJ 300mil 26(24)L SOJ 300mil 26(24)L SOJ 300mil 26(24)L SOJ 300mil 26(24)L SOJ 300mil 26(24)L SOJ 300mil 26(24)L SOJ 300mil 26(24)L SOJ 300mil 26(24)L SOJ 300mil 26(24)L SOJ 300mil 26(24)L SOJ 300mil 26(24)L SOJ 300mil 26(24)L SOJ 300mil 26(24)L SOJ 300mil 26(24)L TSOPII 300mil 26(24)L TSOPII 300mil 26(24)L TSOPII 300mil 26(24)L TSOPII 300mil 26(24)L TSOPII 300mil 26(24)L TSOPII 300mil 26(24)L TSOPII 300mil 26(24)L TSOPII 300mil 26(24)L TSOPII 300mil 26(24)L TSOPII 300mil 26(24)L TSOPII 300mil 26(24)L TSOPII 300mil 26(24)L TSOPII 300mil 26(24)L TSOPII 300mil 26(24)L TSOPII 300mil 26(24)L TSOPII 300mil 26(24)L
G-Link Technology
2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan.
- 20 -
G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
Parts Numbers (Top Mark) Definition :
GLT 4 160 L 04 S E
4 : DRAM 5 : Synchronous DRAM 6 : Standard SRAM 7 : Cache SRAM 8 : Synchronous Burst SRAM 9 : SGRAM
- 40 J3
PACKAGE
T : PDIP(300mil) TS : TSOP(Type I) ST : sTSOP(Type I) TC : TSOPll (40/44) TD : TSOPII (44/50) PL : PLCC FA : 300mil SOP FB : 330mil SOP FC : 445mil SOP J3 : 300mil SOJ J4 : 400mil SOJ P : PDIP(600mil) Q : PQFP TQ : TQFP FG : 48Pin BGA 9x12 FH : 48Pin BGA 8x10 FI : 48Pin BGA 6x8
-SRAM
064 : 8K 256 : 256K 512 : 512K 100 : 1M
CONFIG.
04 : x04 08 : x08 16 : x16 32 : x32
SPEED -SRAM
12 : 12ns 15 : 15ns 20 : 20ns 70 : 70ns
-DRAM
10 : 1M(C/EDO) 11 : 1M(C/FPM) 12 : 1M(H/EDO) 13 : 1M(H/FPM) 20 : 2M(EDO) 21 : 2M(FPM) 40 : 4M(EDO) 41 : 4M(FPM) 80 : 8M(EDO) 81 : 8M(FPM) 160 : 16M(EDO) 161 : 16M(FPM) 640 : 64M(EDO) 641 : 64M(FPM)
-DRAM
25 : 25ns 28 : 28ns 30 : 30ns 35 : 35ns 40 : 40ns 45 : 45ns 50 : 50ns 60 : 60ns 70 : 70ns 80 : 80ns 100 : 100ns SDRAM : 5 : 5ns/200 MHZ 5.5 : 5.5ns/182 MHZ 6 : 7ns/166 MHZ 7 : 8ns/125 MHZ 10 : 10ns/100 MHZ
VOLTAGE
Blank : 5V L : 3.3V M : 2.5V N : 2.1V
-SDRAM
40 : 4M 160 : 16M 320 : 32M,4Bank 321 : 32M,2Bank 640 : 64M
POWER
Blank : Standard S : Self Refresh Low Power L : Low Power LL : Low Low Power SL : Super Low Power
Temperature Range
E : Extended Temperature I : Industrial Temperature Blank : Commercial Temperature
G-Link Technology
2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan.
- 21 -
G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
Package Information
300mil 24/26 Lead Thin Small Outline Package SOJ
300mil 24/26 Lead Thin Small Outline Package (TSOP) TYPE II
G-Link Technology
2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan.
- 22 -

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